1. Field of the Invention
This present invention relates to a semiconductor memory device having a first memory cell array that is used as a regular memory cell array and a second memory cell array a capacity of which is smaller than that of the first memory cell array.
2. Description of the Related Art
As a type of nonvolatile semiconductor memories, there has been heretofore proposed a flash memory capable of electrically erasing data all at once or block by block. In this flash memory, if data is written page by page, it is required to set more data in a memory cell than in an internal bus. For example, when the size (width) of the internal bus is 32 bits and that of data from the outside is 32 bits×64 words=2048 bits, this data of 2048 bits is on the same word line, and this data has to be written into a memory cell at a time. Thus, in order to hold lots of data, a program circuit for the memory cell is required to include a latch circuit for writing (for example, see FIG. 2 of Patent Document 1, Japanese Patent Laid-Open No. Hei 10 (1998)-55688, and the like). However, if the latch circuit for writing is provided, a cell area is increased for this latch circuit. Consequently, in a conventional semiconductor memory, it is difficult to reduce the cell area while realizing processing of vast quantities of data. With reference to the drawings, embodiments of the present invention will be described below. In the description, common components are denoted by common reference numerals and codes throughout the drawings.